On the implementation and optimisation of LDPC codes on a reconfigurable hardware for future communications systems

With the advent of new services and capabilities for next generation mobile communication systems, new powerful error-correcting schemes have emerged to increase cellular capacity and achieve higher transmission data rates effectively. A new set of error-correcting codes (ECCs), called low-density parity check codes (LDPCs), significantly reduce error-rates compared to conventional ECCs. This coding scheme achieves near-Shannon capacity, but unlike other schemes,offers great possibilities for implementation and parallelisation in reconfigurable systems such as field programmable gate arrays (FPGA). FPGA technology offers devices with a large scale of integration. However, the technology mapping stage of logic synthesis is considered not to be optimal enough. We show that evolutionary algorithms, and particularly genetic algorithms, are suitable for the optimisation of technology mapping. These algorithms model natural evolutionary processes, using selection, crossover and mutation operations, and significantly optimise the routing delay in the mapping process compared to commercial automatic mapping tools. A methodology for the implementation of an LDPC encoder/decoder in a commercial FPGA and a genetic algorithm that is used to optimise this implementation is presented. The proposed scheme highlights the potential of evolutionary methods in the reconfigurability of wireless devices.