Title :
iCET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips
Author :
Cheng, Yi-Kan ; Teng, Chin-Chi ; Dharchoudhury, Abhijit ; Rosenbaum, Elyse ; Kang, Sung-Mo
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
In this paper, we present the first chip-level electrothermal simulator, iCET. For a given chip layout, packaging material, user-specified input signal patterns, and thermal boundary conditions, it automatically finds the CMOS on-chip steady-state temperature profile and the resulting circuit performance. iCET has been tested on several circuits and it can efficiently analyze layouts containing tens of thousands of transistors on a desktop workstation
Keywords :
CMOS integrated circuits; VLSI; circuit analysis computing; integrated circuit packaging; integrated circuit reliability; CMOS VLSI chips; chip layout; complete chip-level thermal reliability diagnosis tool; electrothermal simulator; iCET; packaging material; thermal boundary conditions; user-specified input signal patterns; Automatic testing; Boundary conditions; Circuit optimization; Circuit simulation; Circuit testing; Electrothermal effects; Materials testing; Packaging; Steady-state; Temperature;
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-3294-6
DOI :
10.1109/DAC.1996.545636
