Title :
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory
Author :
Chen, Te-Hsuan ; Hsiao, Yu-Ying ; Hsing, Yu-Tsao ; Wu, Cheng-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
ECC has been widely used to enhance flash memory endurance and reliability. In this work, we propose an adaptive-rate ECC scheme with BCH codes that is implemented on the flash memory controller. With this scheme, flash memory can trade storage space for higher error correction capability to keep it usable even when there is a high noise level.
Keywords :
NAND circuits; error correction codes; flash memories; BCH codes; NAND flash memory; adaptive-rate error correction scheme; flash memory controller; high noise level; storage space; Decoding; Encoding; Error correction; Error correction codes; Fault tolerance; Flash memory; Information retrieval; Memory management; Polynomials; Very large scale integration; BCH code; Error correction; flash memory; memory fault tolerance; memory management;
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-0-7695-3598-2
DOI :
10.1109/VTS.2009.24
