Title :
Recursive Path Selection for Delay Fault Testing
Author :
Chung, Jaeyong ; Abraham, Jacob A.
Author_Institution :
Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX, USA
Abstract :
This paper presents a new path selection algorithm for delay fault testing in a statistical timing framework. Existing algorithms which consider correlation between paths use an iterative process for each path or defect and require a Monte Carlo simulation for each iteration to calculate the conditional fault probability. The proposed algorithm does not require the iteration process and selects a requested number of paths simultaneously once it performs a statistical timing analysis at the beginning. If selection of k paths is required in a set of paths, it partitions the set into two path sets and determines how many paths should be selected in each path set out of the k paths. It recursively continues this process and ends up with k paths. The partitioning is easily performed during the recursive traversal of a circuit, which produces an imaginary path tree, where paths are already grouped based on their prefix. Experimental results show the proposed algorithm can effectively use structural correlation and spatial correlation to generate high quality path sets.
Keywords :
Monte Carlo methods; fault trees; iterative methods; recursive estimation; statistical analysis; timing circuits; Monte Carlo simulation; circuit recursive traversal; delay fault testing; imaginary path tree; iterative process; recursive path selection; spatial correlation; statistical timing framework; Algorithm design and analysis; Circuit faults; Circuit testing; Crosstalk; Delay effects; Iterative algorithms; Partitioning algorithms; Probability; Timing; Very large scale integration; Delay Test; Path Selection; Performance Test; Small Delay Defects; Statistical Timing Model;
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-0-7695-3598-2
DOI :
10.1109/VTS.2009.50