Design of an Area Efficient High-Speed Color FDWT Processor

Author

Raghunath, Senthamaraikannan ; Aziz, Syed Mahfuzul

Author_Institution

Sch. of Electr. & Inf. Eng., South Australia Univ., Mawson Lakes, SA

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

474

Lastpage

477

Abstract

A two dimensional discrete wavelet transform processor for color images is presented in this paper. Optimal hardware utilization with minimal CLB slice count and high frequency of operation is achieved in implementing a JPEG2000 standard integer lossless 5/3 filter. Lifting scheme is used to reduce hardware complexity. Image boundaries are handled using the symmetric extension property of the lifting scheme at no extra clock cycle. Synthesizing the proposed architecture for a Xilinx Virtex 2 FPGA, we achieve a maximum frequency of operation of 218.7 MHz utilizing only 478 CLB slices for any input color image of arbitrary size

Keywords

coprocessors; discrete wavelet transforms; field programmable gate arrays; image coding; 218.7 MHz; 2D discrete wavelet transform processor; JPEG2000 standard; Xilinx Virtex 2 FPGA; area efficient FDWT processor; color images; high-speed color FDWT processor; image boundaries; integer lossless 5/3 filter; lifting scheme; optimal hardware utilization; reduced hardware complexity; symmetric extension property; Clocks; Color; Computer architecture; Discrete cosine transforms; Discrete wavelet transforms; Field programmable gate arrays; Filters; Frequency; Hardware; Image coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342492

Filename

4145434