Title :
A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections
Author :
Chun, Sunghoon ; Kim, Yongjoon ; Kim, Taejin ; Kang, Sungho
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.
Keywords :
automatic test pattern generation; electronic engineering computing; integrated circuit interconnections; integrated circuit testing; interconnection topology information; long onchip interconnections; signal integrity fault model; test methodology; test pattern generation method; Circuit faults; Circuit testing; Crosstalk; Fault detection; Integrated circuit interconnections; Signal analysis; Signal detection; Signal generators; Signal processing; Test pattern generators; Fault modeling; signal integrity; test generation;
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-0-7695-3598-2
DOI :
10.1109/VTS.2009.38