• DocumentCode
    2241988
  • Title

    Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study

  • Author

    Turakhia, Ritesh ; Ward, Mark ; Goel, Sandeep Kumar ; Benware, Brady

  • Author_Institution
    LSI Corp., Beaverton, OR, USA
  • fYear
    2009
  • fDate
    3-7 May 2009
  • Firstpage
    167
  • Lastpage
    172
  • Abstract
    Volume diagnostics introduces important means for yield learning as conventional techniques become more expensive and insufficient in identifying systematic yield limiters. Integrating DFM practices within the design flows requires faster identification and ranking of systematic yield limiters in the design. This paper presents a paradigm for identifying outliers in the fail signatures obtained from volume fail data using fail rate prediction from chip-level CAA analysis. Results from case study shows that a comparative analysis between predicted and observed fail rates can highlight potential yield limiters.
  • Keywords
    application specific integrated circuits; design for manufacture; integrated circuit design; chip-level CAA analysis; design for manufacturability; fail rate prediction; fail signatures; industrial ASIC design; outliers; systematic yield limiters; volume diagnostics; yield learning; Computer aided analysis; Data mining; Design for manufacture; Failure analysis; Large scale integration; Manufacturing processes; Process design; Production; System testing; USA Councils; Critical Area Analysis; DFM; Systematic defects; Volume Diagnostics; Yield Learning; Yield Optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2009. VTS '09. 27th IEEE
  • Conference_Location
    Santa Cruz, CA
  • ISSN
    1093-0167
  • Print_ISBN
    978-0-7695-3598-2
  • Type

    conf

  • DOI
    10.1109/VTS.2009.37
  • Filename
    5116628