Title :
Yield and Cost Analysis of a Reliable NoC
Author :
Shamshiri, Saeed ; Cheng, Kwang-Ting
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of California, Santa Barbara, CA, USA
Abstract :
The yield and cost of a multi-core chip improve significantly through the addition of some spare cores in the system. In this paper, we model the manufacturing and service cost of an NoC with spare wires and routers as well as spare cores. We apply our analysis on an exemplary 9-core processor and on an Intel 80-core processor, and show that a spare scheme can significantly improve the reliability, reduce the cost, and substitute for the burn-in process.
Keywords :
costing; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; network-on-chip; Intel 80-core processor; NoC manufacturing; burn-in process; cost analysis; exemplary 9-core processor; multicore chip yield; reliable NoC; Costs; Field programmable gate arrays; Logic devices; Manufacturing processes; Multicore processing; Network-on-a-chip; Programmable logic arrays; Redundancy; Virtual manufacturing; Wires; NoC; SoC; burn-in elimination; cost optimization; distributed redundancy; spare-enhanced resiliency; yield analysis;
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-0-7695-3598-2
DOI :
10.1109/VTS.2009.34
