Title :
A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset
Author :
Jenkins, Keith A. ; Li, Lionel
Author_Institution :
IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
An on-chip circuit to measure static phase offset between a reference signal and the feedback signal of a PLL (phase-locked loop) is designed using only digital elements. It is demonstrated in a 65 nm, 1.0 V CMOS technology. It has a measured resolution of 2 ps and a range of more than +/-100 ps of phase offset and, and consumes 3 mW of power at 1 GHz. It uses an on-chip calibration referred to the reference clock frequency. The measured results are reported through digital scan chains.
Keywords :
CMOS digital integrated circuits; built-in self test; calibration; digital phase locked loops; nanoelectronics; CMOS technology; digital BIST circuit; digital element; digital scan chain; feedback signal; frequency 1 GHz; on-chip calibration; on-chip circuit design; phase-locked loop; power 3 mW; reference clock frequency; scalable circuit; size 65 nm; static phase offset compensation; static phase offset measurement; voltage 1.0 V; Built-in self-test; CMOS technology; Calibration; Feedback circuits; Feedback loop; Phase locked loops; Phase measurement; Power measurement; Signal design; Signal resolution; PLL; built-in self-test; on-chip measurement; phase-locked loop; static phase error; static phase offset;
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-0-7695-3598-2
DOI :
10.1109/VTS.2009.36
