Title :
Design of 3-4GHz Tunable Low Noise LC-QVCO for IEEE 802.11a WLAN Application
Author :
Ramiah, H. ; Zainal, T. ; Zulkifli, A. Z.
Author_Institution :
Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Seberang Prai Selatan
Abstract :
This paper presents the design of a source injection parallel coupled (SIPC) quadrature voltage controlled oscillator (QVCO), realized with pMOS transistor, thus relaxing the sensitivity to substrate-induced noise and flicker noise (1/f) effect. A stacked spiral inductor exhibiting a Q factor of 5.8, with a pMOS based capacitor of 32% in tuning range, corresponding to 3-4GHz of tuning frequency, is implemented in 0.18mum CMOS technology. The phase noise of the SIPC QVCO architecture simulated at 1MHz of offset frequency is indicated to be -113.5 dBc/Hz, in comparison to the phase noise of a conventional QVCO architecture which is indicated to be -110.3dBc/Hz, while dissipating the same amount of power, 14.6mW
Keywords :
1/f noise; CMOS integrated circuits; MMIC oscillators; flicker noise; inductors; phase noise; voltage-controlled oscillators; wireless LAN; 0.18 micron; 1 MHz; 1/f noise; 14.6 mW; 3 to 4 GHz; CMOS technology; IEEE 802.11a; flicker noise; pMOS transistor; phase noise; quadrature voltage-controlled oscillator; source injection parallel coupled quadrature VCO; stacked spiral inductor; wireless LAN; 1f noise; CMOS technology; Frequency; Inductors; MOSFETs; Phase noise; Spirals; Tuning; Voltage-controlled oscillators; Wireless LAN; Phase noise; pMOS capacitor; quadrature voltage-controlled oscillator (QVCO); source injection parallel coupled quadrature VCO (SIPC-QVCO); stacked spiral inductor;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342519
