Title :
Testing for Transistor Aging
Author :
Baba, A. Hakan ; Mitra, Subhasish
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
Transistor aging results in circuit delay degradation over time,and is a growing concern for future systems. On-line circuit failure prediction, together with on-line self-test, can overcome transistor aging challenges for robust systems with built-in self-healing. Effective circuit failure prediction requires very thorough testing to estimate the amount of aging in various parts of a large design during system operation. This paper introduces such testing techniques. Results on large designs demonstrate the practicality and effectiveness of presented techniques.
Keywords :
active networks; ageing; automatic testing; combinational circuits; delays; integrated circuit design; integrated circuit reliability; transistor circuits; circuit delay degradation; online circuit failure prediction; online self test; transistor aging; Aging; Built-in self-test; Circuit testing; Clocks; Degradation; Delay; Niobium compounds; System testing; Timing; Titanium compounds; Delay tests; Failure prediction; Transistor aging; path selection; test pattern generation;
Conference_Titel :
VLSI Test Symposium, 2009. VTS '09. 27th IEEE
Conference_Location :
Santa Cruz, CA
Print_ISBN :
978-0-7695-3598-2
DOI :
10.1109/VTS.2009.56
