• DocumentCode
    2242437
  • Title

    Low power conditional sum adder using pass logic topology

  • Author

    Saleem, Dhia ; Al-Khalili, Dhamin

  • Author_Institution
    Nortel Semicond., Nepean, Ont., Canada
  • Volume
    1
  • fYear
    1998
  • fDate
    24-28 May 1998
  • Firstpage
    9
  • Abstract
    The Low Power Conditional Sum Adder (CSA) has been analyzed using various logic styles. Pass logic topology implementation offered low power delay product and occupied less silicon area compared to other topologies. A test chip for two versions of the CSA using pass logic and standard CMOS has been designed and fabricated using 0.5 μ CMOS technology. Test results indicate that 50% power saving has been achieved in Pass Logic CSA
  • Keywords
    CMOS logic circuits; adders; formal logic; microprocessor chips; CMOS technology; Pass Logic CSA; logic styles; low power conditional sum adder; low power delay product; pass logic topology; pass logic topology implementation; standard CMOS; test chip; Adders; Arithmetic; CMOS logic circuits; CMOS technology; Circuit simulation; Circuit topology; DH-HEMTs; Logic design; Logic devices; Logic testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 1998. IEEE Canadian Conference on
  • Conference_Location
    Waterloo, Ont.
  • ISSN
    0840-7789
  • Print_ISBN
    0-7803-4314-X
  • Type

    conf

  • DOI
    10.1109/CCECE.1998.682537
  • Filename
    682537
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2242437