Parallel architecture of an all digital timing recovery scheme for high speed receivers

In a communication system the receiver has to be synchronized to the incoming data signal in order to rebuild the transmitted data. Therefore a timing recovery circuit is necessary. Most known implementations of this feature assume that in a digital receiver the samples are processed one after another. This is not true for high speed receivers that are clocked at some stage with a rate less than the symbol rate of the incoming signal. In this case, multiple samples have to be handled during one clock cycle, thus parallelization has to be introduced. For such a parallel receiver structure a completely digital timing recovery scheme is proposed, consisting of a sample dropping unit, parallel interpolators and a control loop.