Cleaning after silicon oxide CMP

Author

Tardif, F. ; Mansart, I. ; Lardin, T. ; Demolliens, O. ; Fayolle, M. ; Gobile, Y. ; Palleau, J. ; Torres, J.

Author_Institution

CEA, Centre d´´Etudes Nucleaires de Grenoble, France

fYear

1997

fDate

16-19 March 1997

Firstpage

74

Lastpage

77

Abstract

With the decrease of the device dimensions, back-end layer planarisation by Chemical Mechanical Polishing (CMP) seems now absolutely necessary for technologies down to 0.35 /spl mu/m. CMP processes induce billions of particles, parasitic metallic contaminations and a damaged layer at the top surface of the dielectrics. It is therefore necessary to add a new powerful cleaning process after each CMP step which was not necessary in the past. We early defined the general concepts of cleanings adapted to back-end steps. We propose here to apply our previous results to the practical case of PECVD TEOS oxide CMP where SiO/sub 2/ slurries are used.

Keywords

dielectric thin films; plasma CVD coatings; polishing; silicon compounds; surface cleaning; 0.35 micron; PECVD TEOS silicon oxide; SiO/sub 2/; SiO/sub 2/ slurry; back-end step; chemical mechanical polishing; cleaning; damaged layer; dielectric surface; metallic contamination; particle contamination; planarisation; Chemical technology; Cleaning; Dielectrics; Hafnium; Inorganic materials; Metallization; Planarization; Silicon; Slurries; Surface contamination;

fLanguage

English

Publisher

ieee

Conference_Titel

Materials for Advanced Metallization, 1997. MAM '97 Abstracts Booklet., European Workshop

Conference_Location

Villard de Lans, France

ISSN

1266-0167

Type

conf

DOI

10.1109/MAM.1997.621064

Filename

621064