Title :
A 670 ps, 64 bit dynamic low-power adder design
Author :
Woo, Ramchan ; Lee, Se-Joong ; Yoo, Hoi-Jun
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Abstract :
A 64 bit dynamic low-power adder has been designed and fabricated for 2.5 V 0.25-μm 1-poly 5-metal CMOS technology. Fast carry propagation is obtained by fast P generation, parallel quaternary-tree form of group carry (GC) selection and conditional sum selection. The results of proposed adder architecture show that propagation delay, power consumption, and the area are 670 ps, 100 mW, and 0.16 mm2 , respectively
Keywords :
CMOS logic circuits; adders; digital arithmetic; logic design; low-power electronics; 0.25 micron; 1-poly 5-metal CMOS technology; 100 mW; 2.5 V; 64 bit; 670 ps; adder architecture; carry propagation; conditional sum selection; dynamic low-power adder design; group carry selection; parallel quaternary-tree form; propagation delay; Adders; CMOS technology; Circuit synthesis; Energy consumption; Frequency; Laboratories; Microprocessors; Propagation delay; Signal generators; Wiring;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857017
