DocumentCode :
2243300
Title :
Detailed Behavioral Modeling of Bang-Bang Phase Detectors
Author :
Jiang, Chenhui ; Andreani, Pietro ; Keil, Ulrich D.
Author_Institution :
OErsted-DTU, Denmark Tech. Univ., Lyngby
fYear :
2006
fDate :
4-7 Dec. 2006
Firstpage :
716
Lastpage :
719
Abstract :
In this paper, the metastability of current-mode logic (CML) latches and flip-flops is studied in detail. Based on the results of this analysis, a behavioral model of bang-bang phase detectors (BBPDs) is proposed, which is able to reliably capture the critical deadzone effect. The impact of jitter and of process, voltage and temperature variations on the BBPD behavior is also investigated. The proposed model can be used with advantage in the high-level design and verification of e.g. clock and data recovery (CDR) circuits
Keywords :
current-mode logic; flip-flops; jitter; phase detectors; synchronisation; bang-bang phase detectors; clock and data recovery circuits; current-mode logic latches; flip-flops; high-level design; jitter; metastability; Clocks; Detectors; Flip-flops; Jitter; Latches; Logic; Metastasis; Phase detection; Temperature; Voltage; Bang-Bang phase detector; behavioral model; deadzone; jitter; metastability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
Type :
conf
DOI :
10.1109/APCCAS.2006.342108
Filename :
4145493
Link To Document :
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