Design Partitioning for Reducing Crosstalk Analysis Time

With increasing complexity of designs and reducing process nodes, the number of devices in designs has been rapidly rising. This has a dramatic impact on analysis of these designs, as the software and hardware are unable to analysis such designs "flat". The authors discuss a method for partitioning designs so that crosstalk analysis can be done on these smaller partitions and show that the technique cleanly divides the netlist into independent problem statements that can be analyzed parallely. The authors also show that the results of such independent runs can be merged and that the final report of the analysis is accurate (as compared to the analysis on the complete design). The authors show that the technique provides for dramatic reductions in runtime, and that the memory requirements of the design are also partitioned across the machines in approximately the same ratio as the size of the partitions themselves