Title :
A low power VLSI architecture of SOVA-based turbo-code decoder using scarce state transition scheme
Author :
Wang, Yan ; Tsui, Chi-ying ; Cheng, Roger S.
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
Abstract :
In this paper, we propose a low power VLSI architecture of Soft-Output-Viterbi-Algorithm (SOVA) based turbo-code decoder using a scarce state transition scheme (SST). A register exchange survival memory unit (RE-SMU) and systolic block are used in the implementation of SOVA for high throughput and low latency. SST is used to reduce the power consumption. Simulation results show that the power consumption of RE-SMU and the systolic block is reduced significantly. The power consumption of the add-compare-select (ACS) block is also reduced by as much as 20% after 4 iterations of turbo-code decoding
Keywords :
VLSI; Viterbi decoding; codecs; digital signal processing chips; low-power electronics; systolic arrays; turbo codes; ACS block; DSP chip; SOVA-based turbo-code decoder; W-CDMA; add-compare-select block; low power VLSI architecture; power consumption reduction; register exchange survival memory unit; scarce state transition scheme; soft output Viterbi algorithm; systolic block; wideband CDMA; Codecs; Delay; Energy consumption; Iterative decoding; Multiaccess communication; Systolic arrays; Throughput; Turbo codes; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857085
