A dataflow-oriented VLSI architecture for a modified SPIHT algorithm using depth-first search bit stream processing

In this paper, we present a dataflow-oriented architecture for a modified SPIHT algorithm which is suitable for VLSI implementation. The input into the architecture is a bit stream of the wavelet coefficients in the depth-first search (DFS) format and the output from the architecture is a data stream containing the significance map (MAP) and successive-approximation quantization (SAQ) symbols for the SPIHT algorithm. The memory requirements for the architecture are reduced by transmitting the MAP and SAQ symbols as they are generated. The MAP and SAQ symbols are formulated in view of the DFS coefficient bit stream and the corresponding VLSI architecture to implement the formulated requirements is presented. Simulations are also presented to compare the coding efficiency for the modified SPIHT architecture versus the complete SPIHT algorithm