DocumentCode
2244398
Title
An ordering-insensitive methodology for efficient DCVS circuit synthesis
Author
Armah, A. ; Jaekel, A.
Author_Institution
Sch. of Comput. Sci., Windsor Univ., Ont., Canada
Volume
1
fYear
1998
fDate
24-28 May 1998
Firstpage
49
Abstract
Reduced ordered binary decision diagrams (ROBDDs) have been used for the synthesis of differential cascode voltage switch (DCVS) circuits. ROBDDs require all branches of the resultant network to have the same input ordering. Significant improvements in area can be obtained by allowing each branch of the network to have a different variable ordering, if needed. In this paper, we outline our synthesis procedure, which uses a new decision-diagram based model, the 123 decision diagram (123dd), to synthesize DCVS circuits. These circuits may have different variable orderings on different branches of the network
Keywords
Boolean functions; integrated logic circuits; logic CAD; 123 decision diagram; DCVS circuit synthesis; differential cascode voltage switch; ordering-insensitive methodology; reduced ordered binary decision diagrams; variable ordering; Arithmetic; Boolean functions; Circuit synthesis; Computer science; Data structures; Digital signal processing; Network synthesis; Switches; Switching circuits; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 1998. IEEE Canadian Conference on
Conference_Location
Waterloo, Ont.
ISSN
0840-7789
Print_ISBN
0-7803-4314-X
Type
conf
DOI
10.1109/CCECE.1998.682547
Filename
682547
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