DSP implementation of very low bit rate videoconferencing system

Author

Tye, B. ; Goh, K. ; Lin, W. ; Powell, G. ; Ohya, T. ; Adachi, S.

Author_Institution

Inst. of Microelectron., Singapore

Volume

3

fYear

1997

fDate

9-12 Sep 1997

Firstpage

1275

Abstract

A real-time full-duplex videoconferencing system using parallel DSPs is described. Effective strategies for H.263 video coding have been developed to improve the efficiency of the system. Further speed-up is achieved by utilising multiple DSP processors. The video codec is integrated with a G.723.1 speech codec to form an H.324 compliant bitstream, using H.223 multiplex and H.245 control protocols

Keywords

code standards; data compression; digital signal processing chips; parallel processing; protocols; speech codecs; telecommunication standards; teleconferencing; video codecs; video coding; G.723.1 speech codec; H.223 multiplexing protocol; H.245 control protocols; H.263 video coding; H.324 compliant bitstream; multiple DSP processors; parallel DSP; real-time full-duplex videoconferencing; system efficiency; very low bit rate videoconferencing system; video codec; video compression; Bit rate; Digital signal processing; Electronic mail; Real time systems; Spirals; Teleconferencing; Video codecs; Video coding; Video compression; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Information, Communications and Signal Processing, 1997. ICICS., Proceedings of 1997 International Conference on

Print_ISBN

0-7803-3676-3

Type

conf

DOI

10.1109/ICICS.1997.652192

Filename

652192