Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate

Fine-grain sleep transistor insertion (FGSTI) technique is easier to guarantee circuit functionality and improves circuit noise margins while achieves a considerable leakage saving when the circuit is standby. However, when the circuit slowdown is not enough to assign sleep transistors (ST) to each gate, a large amount of leakage feedback (LF) gates should be used to avoid floating states, and these additional buffers will induce large area and dynamic power penalty. In this paper, we propose a multi-object optimization method to simultaneously reduce the LF gate number and the leakage current. Our experimental results show that, when the circuit slowdown varies from 0% to 5%, comparing with method only considering the leakage current reduction, we can achieve on average 4times-9times LF gate number reduction while the leakage difference is only about 8% of original circuit leakage