Design Considerations of Ultralow-Voltage Self-Calibrated SAR ADC

This brief presents a 0.5-V 11-bit successive approximation register analog-to-digital converter (ADC) with a focus on self-calibration at a low supply voltage. The relationships among the noise of comparators, the resolution of a calibration digitalto-analog converter (DAC), and the overall ADC performance are studied. Analysis shows that the nonlinearity of a calibration DAC and a coupling capacitor has an insignificant effect. An ultralow-leakage switch is also described, and an improved process of measuring mismatch is proposed to alleviate the charge injection of a sampling switch. Fabricated in the 0.13-μm CMOS with an active area of 0.868 mm², the ADC achieves a signal-to-noise-plus-distortion ratio (SNDR) of 62.12 dB and a spurious-free dynamic range of 73.03 dB at a 500-kS/s sampling rate. The power consumption is 39.9 μW.