• DocumentCode
    2245252
  • Title

    VSIP : Implementation of Video Specific Instruction-set Processor

  • Author

    Kim, Sung D. ; Hyun, Choong J. ; Sunwoo, Myung H.

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon
  • fYear
    2006
  • fDate
    4-7 Dec. 2006
  • Firstpage
    1075
  • Lastpage
    1078
  • Abstract
    With the rapid progress of semiconductor technology, application specific instruction-set processor (ASIP), which adopts high performance and low power of ASIC and flexibility of DSP, has become increasingly important. In this paper, the video specific instruction-set processor (VSIP) is presented. VSIP has special instructions and co-processors for computation intensive parts in video signal processing, such as inter prediction, entropy coding, de-blocking filter, etc. The proposed VSIP has been thoroughly verified using an FPGA board having the Xilinxtrade Virtex II. The proposed VSIP can implement a H.264/AVC decoder. The proposed VSIP is one of promising solutions for video signal processing
  • Keywords
    coprocessors; decoding; field programmable gate arrays; instruction sets; ASIP; FPGA board; H.264/AVC decoder; VSIP; application specific instruction-set processor; co processors; video signal processing; video specific instruction-set processor; Application specific integrated circuits; Application specific processors; Automatic voltage control; Computer aided instruction; Coprocessors; Digital signal processing; Entropy coding; Field programmable gate arrays; Filters; Video signal processing; Application Specific instruction-set Processor (ASIP); H.264/AVC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
  • Conference_Location
    Singapore
  • Print_ISBN
    1-4244-0387-1
  • Type

    conf

  • DOI
    10.1109/APCCAS.2006.342307
  • Filename
    4145583