Title :
Inertial and degradation delay model for CMOS logic gates
Author :
Juan-Chico, J. ; De Clavijo, P. Ruiz ; Bellido, M.J. ; Acosta, A.J. ; Valenia, M.
Author_Institution :
Inst. de Microelectron. de Sevilla, Spain
Abstract :
The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the degradation delay model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches
Keywords :
CMOS logic circuits; circuit simulation; digital simulation; integrated circuit modelling; logic gates; logic simulation; CMOS logic gates; IDDM model; arbitrarily narrow pulses; digital simulation; glitches; inertial and degradation delay model; inertial effect; CMOS logic circuits; Circuit simulation; Degradation; Delay effects; Filtering; Logic gates; Propagation delay; Semiconductor device modeling; Space vector pulse width modulation; Timing;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.857130
