New Reconfiguration Algorithm for Degradable VLSI Arrays

A new rerouting approach is proposed in this paper for the reconfiguration of two-dimensional degradable VLSI arrays under the constraint of row and column rerouting. The proposed approach chooses the local best processing element in each step to construct the leftmost logical columns, in order to utilize as many non-faults lying in the excluded rows as possible to enlarge the harvest of the algorithm. A more efficient reconfiguration algorithm is obtained by replacing the old rerouting approach with the new one. Experimental results clearly demonstrate the notable improvements in harvest over the most efficient algorithm cited in the literature. The harvest improvement increases with the increase of fault size, both for maximal target arrays and maximal square target arrays