DocumentCode
2245788
Title
Scalable implementation of H.263 video encoder on a parallel DSP system
Author
Kolinummi, Pasi ; Sarkijarvi, J. ; Hamalainen, Timo ; Saarinen, Jukka
Author_Institution
Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland
Volume
1
fYear
2000
fDate
2000
Firstpage
551
Abstract
A parallel implementation of H.263 video encoder is presented for video conferencing applications. The parallel mapping has low communication and memory requirements and is scalable, which allows encoding of any of the five standard H.263 picture formats in real-rime. The presented parallelization method is implemented in a linearly expandable multiprocessor system called PARNEU, which includes very versatile communication topology. With the prototype system using four ADSP-21062 DSPs, a real-time encoding is achieved with QCIF sized picture. Performance estimations given for a larger system show very good speed-up figures
Keywords
digital signal processing chips; multiprocessing systems; parallel processing; teleconferencing; video coding; ADSP-21062 DSP; H.263 video encoder; PARNEU; QCIF picture; communication topology; multiprocessor system; parallel mapping; real-time encoding; video conferencing; Concurrent computing; Digital signal processing; Digital signal processing chips; Digital signal processors; Encoding; Field programmable gate arrays; Real time systems; Signal processing algorithms; Video compression; Videoconference;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location
Geneva
Print_ISBN
0-7803-5482-6
Type
conf
DOI
10.1109/ISCAS.2000.857154
Filename
857154
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