Matrix Inversion on Reconfigurable Hardware using Binary-coded z-path CORDIC

Modern digital signal processing and communications often involve computational demanding algorithms to deal with large matrix problems such as matrix multiplication and inversion. Traditional solutions with digital signal processors (DSP) or general purpose processors (GP) are time consuming and the computation latency can grow exponentially when the problem size increases. An alternative way is application specific integrated circuit (ASIC). The data are processed in the parallel hardware with single instruction multiple data (SIMD) fashion. But the production time is critically high, which usually takes one or two years before the final fabrication, and once the chip is fabricated the structure has no flexibility when the application changes. With today´s ever increasing integrated density, reconfigurable hardware shows a promising solution for these computation demanding problems. In this paper, a scalable and pipelined matrix inversion structure targeting on reconfigurable hardware is presented by adopting an novel binary-coded z-path coordinated rotation digital computer (Bi-z CORDIC) to save hardware consumption and increase the data throughput