11.4 Gb/s multiplexer for future broadband communications networks

Author

Bagheri, Mehran ; Holden, Wayne S.

Author_Institution

Bellcore, Red Bank, NJ, USA

fYear

1989

fDate

18-19 Sep 1989

Firstpage

291

Lastpage

294

Abstract

The authors discuss a 2:1 multiplexer operating from 100 Mb/s to 11.4 Gb/s, which was fabricated using a silicon nitride self-aligned process that features 0.6-μm-wide arsenic-doped emitters with 4-μm base-to-base pitch, deep trench isolation, 2-μm-thick field oxide isolation, polysilicon resistors, and a two-layer TiW-Au metallization. This technology produces transistors with a cutoff frequency (f _t) of 10-15 GHz. The chip measures 0.9×0.8 mm², dissipates 350 mW with a 5-V supply, and operates at the fastest data rate reported to date for a multiplexer in any IC technology

Keywords

bipolar integrated circuits; digital integrated circuits; multiplexing equipment; 0.6 micron; 10 to 15 GHz; 11.4 to 100 Mbit/s; 2 micron; 2:1 multiplexer; 350 mW; 4 micron; Au-TiW; IC technology; Si; base-to-base pitch; broadband communications networks; cutoff frequency; data rate; deep trench isolation; field oxide isolation; polysilicon resistors; self-aligned process; Availability; Bit rate; Broadband communication; Communication networks; Driver circuits; Low voltage; Multiplexing; SONET; Silicon; Standards development;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1989.69511

Filename

69511