Title :
A digitally programmable delay chip with picosecond resolution
Author :
Sakamoto, K. ; McDonald, J. ; Swapp, M. ; Weir, B.
Author_Institution :
Motorola Inc., Mesa, AZ, USA
Abstract :
A digitally programmable delay chip fabricated on MOSAIC III, an advanced bipolar process, is described. The CML/ECL-based design comprises a digitally programmable delay chain and an analog vernier adjustment to achieve high-resolution capability. The architecture and fabrication process are described. Results from a test vehicle have demonstrated an average coarse step size of 110 ps and a fine tune resolution of 0.5 ps. A production version with improved linearity and reduced delay variation with temperature has been developed
Keywords :
bipolar integrated circuits; delay circuits; digital integrated circuits; integrated circuit technology; CML/ECL-based design; MOSAIC III; advanced bipolar process; analog vernier adjustment; coarse step size; delay variation; digitally programmable delay chip; fabrication process; fine tune resolution; high-resolution capability; linearity; picosecond resolution; Automatic control; Circuits; Clocks; Delay; Digital control; Joining processes; Latches; Multiplexing; Test equipment; Voltage;
Conference_Titel :
Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989
Conference_Location :
Minneapolis, MN
DOI :
10.1109/BIPOL.1989.69512
