DocumentCode :
2246167
Title :
Design and implementation of an EPLD-based variable length coder for real time image compression applications
Author :
Ramachandran, S. ; Srinivasan, S.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India
Volume :
1
fYear :
2000
fDate :
2000
Firstpage :
607
Abstract :
This paper proposes an effective implementation of Variable Length Coder (VLC) for image compression using an Embedded Programmable Logic Device (EPLD) to meet the real time requirements. The scheme has features such as header information and color processing not found in earlier implementations. It has a throughput of 50 Mbps at 50 MHz clock rate. The design fits into just one piece of a commercially available EPLD and is capable of processing monochrome images of sizes up to 1024×768 pixels and color images of up to 67% of this size, both at the rate of 25 frames per second
Keywords :
colour; data compression; digital signal processing chips; image coding; programmable logic devices; real-time systems; variable length codes; video coding; 1024 pixel; 50 MHz; 50 Mbit/s; 768 pixel; 786432 pixel; EPLD-based variable length coder; colour images; colour processing; embedded PLD; embedded programmable logic device; header information; monochrome images; real time image compression; Bit rate; Clocks; Color; Discrete cosine transforms; Image coding; Throughput; Transform coding; Very large scale integration; Video compression; Videoconference;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
Type :
conf
DOI :
10.1109/ISCAS.2000.857168
Filename :
857168
Link To Document :
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