DocumentCode :
2246427
Title :
Width and Timing-Constrained Wire Sizing for Critical Area Minimization
Author :
Yan, Jin-Tai ; Chiang, Bo-Yi ; Huang, Shi-Qin
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Chung-Hua Univ., Hsinchu
fYear :
2006
fDate :
4-7 Dec. 2006
Firstpage :
1276
Lastpage :
1279
Abstract :
In this paper, given a rectilinear Steiner tree (RST) with timing and width constraints, based on the concept of timing-consistent wire widening for any wire segment, the width of any wire segment may be replaced with its timing-consistent width without destroying the timing constraint of any sink. Furthermore, according to a given particle defect size and the width constraint of any wire segment in the RST, the widths of all the wire segments are reassigned to minimize total routing area of the RST and satisfy all the width and timing constraints for critical area minimization by running a timing-constrained wire sizing process. The experimental results show that our proposed width-and-timing-constrained wire sizing (WTWS) approach increases about 46%~50% total routing area to reduce 77%~84% critical area for the tested routing nets
Keywords :
circuit optimisation; integrated circuit design; integrated circuit interconnections; integrated circuit yield; minimisation; trees (mathematics); critical area minimization; rectilinear Steiner tree; timing constraints; width constraints; width-and-timing-constrained wire sizing; wire widening; Clocks; Computer science; Delay; Lithography; Manufacturing processes; Routing; Steiner trees; Testing; Timing; Wire; critical area; timing constraint; wire sizing; yield;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
Type :
conf
DOI :
10.1109/APCCAS.2006.342396
Filename :
4145633
Link To Document :
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