Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline

Author

Johguchi, K. ; Zhu, Z. ; Mattausch, H.J. ; Koide, T. ; Hironaka, T. ; Tanigawa, K.

Author_Institution

Res. Center for Nanodevices & Syst., Hiroshima Univ., Higashi-Hiroshima

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1297

Lastpage

1300

Abstract

The presented unified data/instruction cache architecture, based on multiple banks, realizes the features of multiple ports, distributed crossbar, different wordlength for data and instruction ports, interleaved cache-line words and synchronous access with hidden precharge. A 4-port, 20.5 Kbyte test chip in CMOS logic technology with 200 nm minimum gate length and 5 metal layers has a 3.4 ns access-cycle time. The access bandwidth corresponds to 10 ports with standard wordlength, while the cost in increased Si-area is only 25%

Keywords

CMOS logic circuits; SRAM chips; cache storage; logic design; multiport networks; silicon; 20.5 kByte; 200 nm; 3.4 ns; CMOS logic technology; SRAM; Si; data-instruction cache; hidden precharge pipeline; multiport architecture; register file; Bandwidth; Bismuth; CMOS logic circuits; CMOS technology; Computer architecture; Decoding; Logic testing; Pipelines; Random access memory; Registers; SRAM; multi-port memory; processor; register file;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342421

Filename

4145638