Multiple-valued SRAM with FG-MOSFETs

In this paper, we propose a novel multiple-valued SRAM cell composed of floating gate-MOSFETs (FG-MOSFET). The proposed circuit can memorize multiple signals per memory cell, and effective to use it as SRAM cell with a multiple-valued logic system. The proposed circuit is the multiple-valued SRAM cell that can be composed of a little number of elements by using the FG-MOS level shift circuit. Securing the noise margin is a very important problem because a multiple-valued logical system is weaker to the noise than a binary logical system. The proposed circuit can secure a steady noise margin in low power-supply voltage. And it is low power consumption. In verification using HSPICE simulations, each stable state can secure a steady noise margin of 0.7V or more for the four-valued SRAM cell with 3V power-supply. The proposed circuit is designed by using the device parameter of the standard CMOS 1.2mum process. The performance of multiple-valued SRAM is evaluated by HSPICE simulation