Circuit modeling technique of electronic package considering S-parameters measurement environments

Generally, in order to extract electrical circuit parameters of package, specific test fixtures composed of short, open, and thru patterns are required. However, electrical parasitic of the test fixtures makes it difficult to extract accurate circuit parameters of the package. In addition to this the values of the parameters are different according to the electrical configurations of adjacent pins like floating, dc biasing, and applying RF signal. In this paper, we presented a new modeling technique of electronic package considering measurement environments. Electrical parasitic components effect on capacitance and inductance of the package are considered in the proposed modeling technique. The modeling technique is verified through comparison between the measured S-parameter by VNA and the results by AC analysis