DocumentCode
2246872
Title
Design of Interconnected Bus for Low Power Based on Boolean Process
Author
Li, Donghai ; Ma, Guangsheng ; Feng, Gang
Author_Institution
Coll. of Comput. Sci. & Technol., Harbin Eng. Univ., Heilongjiang
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
1346
Lastpage
1349
Abstract
In this paper, the authors propose an interconnected bus power consumption model based on Boolean process, which includes the self transition power dissipated on the signal lines and the coupled transition power dissipated between adjacent signal lines. A heuristic algorithm is presented to determine a physical order of signal lines and adjust the distance between adjacent signal lines. Simulation results show that the proposed technique achieves better reduction in terms of power consumption compared to existing methods
Keywords
Boolean algebra; low-power electronics; power consumption; system buses; Boolean process; adjacent signal lines; heuristic algorithm; interconnected bus; low power; power consumption; power optimization; Capacitance; Computer science; Coupling circuits; Educational institutions; Energy consumption; Integrated circuit interconnections; Power dissipation; Signal design; Signal processing; Very large scale integration; Boolean process; interconnected bus; power optimization;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342433
Filename
4145650
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