Implementation of a Symbolic Circuit Simulator for Topological Network Analysis

Many topological approaches to symbolic network analysis have been proposed in the literature, but none are implemented ultimately as a simulator for large network analysis due to their complexity and exponentially increasing number of terms. A novel methodology adopted in this paper uses a graph reduction approach based on a set of graph reduction rules developed recently. Furthermore, a binary decision diagram is used in the implementation of a symbolic simulator that is capable of analyzing large analog circuit blocks. Implementation details and experimental results are reported