Title :
Optimum Supply and Threshold Voltages and Transistor Sizing Effects on Low Power SOI Circuit Design
Author :
Emadi, M. ; Jafargholi, A. ; Moghadam, H. Sargazi ; Nayebi, M.M.
Author_Institution :
Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran
Abstract :
This work introduces a new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of Vdd=0.1- 1.5V and Vth= 0 - 0.8V, are analyzed to find optimal Vdd and Vth. BSIMSOI3.3 model (level 57) is used to verify the answers. The authors show that energy-delay product (EDP) isn´t appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and the formulations for finding the optimum gate sizing are also presented. Theses algorithms can be implemented in a CAD tool too
Keywords :
CMOS integrated circuits; integrated circuit modelling; low-power electronics; network synthesis; silicon-on-insulator; 0 to 1.5 V; 80 nm; CAD tool; EDP contour; SOI-CMOS circuits; design flowcharts; energy-delay product; gate sizing problem; low power SOI circuit design; low power design; optimum supply voltage; threshold voltages; transistor sizing effects; CMOS technology; Circuit synthesis; Degradation; Delay; Energy consumption; MOSFETs; Power dissipation; Silicon on insulator technology; Threshold voltage; Very large scale integration; EDP contour; Energy-delay product; Low power design; Transistor sizing;
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
DOI :
10.1109/APCCAS.2006.342461
