High-Level Synthesis for Self-Timed Systems

We present a tool for high-level synthesis of self-timed system based on the proposed synthesis flow, which allows designers to proceed with asynchronous design by converting channel-level to four-phase handshaking-level HDL without prior knowledge of it. The merit of tool is we take logic-drive approach to tear the commonly-seen algorithmic-level system specification apart into extended burst-mode controllers and self-timed datapath. The controllers can be synthesized by the existing burst-mode synthesis tools such as 3D, ATACTS, XBM2PLA, Minimalist, and so forth. Based on the choice of the circuit implementation, our tool can further transform the minimized hazard-free logic equations to synthesizable HDL specification for FPGA or transistor netlist for fully custom designs. Because of the simplistic nature of the channel-level design style and the flexibility of the FPGA, the proposed synthesis tool can be utilized for rapid prototyping and teaching of asynchronous systems