Title :
Submesh allocation in heterogeneous chip multiprocessors
Author :
Zuo, Qi ; Qiu, Jing
Author_Institution :
High Performance Embedded Comput. Libr., Beijing Inst. of Technol., Beijing, China
Abstract :
Lots of submesh allocation strategies are devised in mesh connected computers. In chip multiprocessors connected by network on chip, submesh allocation is also used to allocate processors. Existing research mainly focuses on fragmentation, system performance and algorithmic complexity. The processors are assumed to be homogeneous, and the representation of them only reflects the state of processors usage, free or allocated. However, heterogeneous cores have been widely adopted in modern chip multiprocessors to better support the different computation needs. Therefore, the submesh allocation should be re-designed to reflect the difference between cores in heterogeneous chip multiprocessors. In this paper, a simple submesh allocation strategy based on processor array is presented. The strategy represents the heterogeneous processors by computing power array and usage bitmap. The jobs are represented by needed computing power array. A constrained first fit algorithm is devised to map jobs to the chip multiprocessors.
Keywords :
multiprocessing systems; network-on-chip; algorithmic complexity; fragmentation; heterogeneous chip multiprocessors; mesh connected computers; network on chip; processor array; submesh allocation; system performance; Algorithm design and analysis; Arrays; Computers; Instruction sets; Machine learning; Resource management; Heterogeneous chip multiprocessor; Submesh allocation;
Conference_Titel :
Machine Learning and Cybernetics (ICMLC), 2010 International Conference on
Conference_Location :
Qingdao
Print_ISBN :
978-1-4244-6526-2
DOI :
10.1109/ICMLC.2010.5580661