Substrate designs to improve die crack damage in CSP

For development and design of high performance ICs, more and more functions are required to be contained in a chip scale package (CSP) for applications that require low profiles and small footprints. With thinner package profile requirements, thinner substrates are necessary. More reliability issues arise with thinner substrates to provide mechanical support. The different kinds of substrate design layout induce different stress distributions which affect the IC directly during various assembly processes. These propagating effects may finally cause die crack damage. Therefore, proper substrate layout design does not only achieve thermal and electrical functional requirements, but also prevents critical mechanical problems. The purpose of this paper is to investigate mechanical effects on the IC of different substrate design patterns. Furthermore, to improve the influence of the optimal substrate layout, a dummy copper layer is used within the substrate. For comparison and confirmation of these phenomena, both numerical analysis (FEA) and experiment measurements were employed. CSPs were used as the test vehicle. Effects of dummy patterns were observed during the assembly process. There is no chip damage observed with modified substrate design. For further investigation of other possible factors, substrate thickness was varied in the FEA model. It was proved that the design effect is insignificant with thicker substrates. A similar result was observed with parameters of chip thickness, and Moire interferometry was engaged to verify FEA models