DocumentCode
2247519
Title
Analysis and Design of High Performance, Low Power Multiple Ports Register Files
Author
Jau, Ting-Sheng ; Yang, Wei-Bin ; Chang, Chung-Yu
Author_Institution
Dept. of SOC Technol. Center, Ind. Technol. Res. Inst., Hsinchu
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
1453
Lastpage
1456
Abstract
This paper talks about how to analyze and design high performance low power multiple-ports register file circuitry, which is mostly used on mu-P and DSP chip. Firstly, in this paper, we discuss basic concept of register files. Secondly we introduce the different types of register file architecture. Then we analyze and compare design trade-offs among those approaches. With that, we decide the suitable register file circuitry for our application. Then, we start to analyze the low power design style for each block. Finally, we achieve design goal of low power and high performance register file circuit compare to some other designs. It is fabricated by TSMC 0.13mum 1p8m 1.2v process. Simulation result shows the design has the fine 0.013 mW/MHz-port
Keywords
digital signal processing chips; integrated circuit design; low-power electronics; reduced instruction set computing; 0.13 micron; 1.2 V; DSP chip; RISC processor; TSMC 0 1p8m process; differential-end structure; high performance register files circuitry; low power design; mu-P chip; multiple ports register file circuitry; single-end structure; Circuit simulation; Decoding; Digital signal processing; Digital signal processing chips; Energy consumption; Flip-flops; Performance analysis; Reduced instruction set computing; Registers; Sleep; DSP; RISC processor; differential-End structure; register file; single-End structure;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342495
Filename
4145676
Link To Document