DocumentCode :
2247676
Title :
2PADCL: Two Phase drive Adiabatic Dynamic CMOS Logic
Author :
Takahashi, Yasuhiro ; Fukuta, Youhei ; Sekine, Toshikazu ; Yokoyama, Michio
Author_Institution :
Dept. of Electr. & Electron. Eng., Gifu Univ.
fYear :
2006
fDate :
4-7 Dec. 2006
Firstpage :
1484
Lastpage :
1487
Abstract :
This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and resembles behavior of static CMOS. As a result, the delay time of the 2PADCL is shorter than that of the conventional ADCL circuit in the second and subsequent stages. The structure of 2PADCL can be also directly derived from static CMOS logic circuits. From the simulation results, we show that the energy consumption of the 2PADCL circuit is lower than those of other diode based adiabatic logic circuits
Keywords :
CMOS logic circuits; driver circuits; low-power electronics; 2PADCL; adiabatic dynamic CMOS logic circuit; complementary sinusoidal power supply clocks; low power logic circuit; static CMOS logic circuits; two-phase power supply; CMOS logic circuits; Clocks; Delay effects; Diodes; Energy consumption; Inverters; Logic circuits; Power engineering and energy; Power supplies; Voltage; adiabatic logic; low power; two-phase power supply;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location :
Singapore
Print_ISBN :
1-4244-0387-1
Type :
conf
DOI :
10.1109/APCCAS.2006.342503
Filename :
4145684
Link To Document :
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