DocumentCode
2247723
Title
An Area-Efficient Design for Modular Inversion in GF(2m)
Author
Wang, Jian ; Jiang, Anping
Author_Institution
Dept. of Microelectron., Beijing Univ.
fYear
2006
fDate
4-7 Dec. 2006
Firstpage
1496
Lastpage
1499
Abstract
Modular inversion is one of the kernel arithmetic operations in error control codes and cryptography, so the design of the low-cost and high-speed hardware implementation is absolutely necessary. A novel algorithm and hardware implementation for modular inversion in finite fields GF(2m) with the standard basis representation is presented. The algorithm used is based on a modification of the extended Euclid´s algorithm. The proposed architecture is O(m) area complexity and O(m) time complexity. It is highly regular, modular and thus well suited to VLSI implementation. Compared with two related architectures with the same time complexity, it can save at least 22.5% combinational area
Keywords
Galois fields; VLSI; cryptography; digital arithmetic; digital circuits; error correction codes; Galois field; area-efficient design; cryptography; error control codes; extended Euclid algorithm; finite fields GF(2m); hardware implementation; kernel arithmetic operations; modular inversion; Algorithm design and analysis; Arithmetic; Computer architecture; Cryptography; Error correction; Galois fields; Hardware; Microelectronics; Polynomials; Very large scale integration; Euclid´s algorithm; Galois Field; VLSI implementation; modular inversion;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Conference_Location
Singapore
Print_ISBN
1-4244-0387-1
Type
conf
DOI
10.1109/APCCAS.2006.342506
Filename
4145687
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