Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits

An efficient logic synthesis based on pass-transistor logic (PTL) is developed which can generate both combinational and sequential circuits. Instead of using traditional CMOS cell library which usually contains hundred of different types of cells, the proposed PTL synthesizer uses only three types of cells: 2-to-1 multiplexer (MUX), inverter, and D flip-flop (DFF). The PTL synthesizer first employs Synopsys design compiler (DC) to perform preliminary logic translation and minimization for the input HDL descriptions. Then, the PTL-based logic mapping performs area reduction and automatic driving strength selection considering user´s area and/or speed requirements. The area reduction process eliminates redundant inverters during PTL logic mapping. The driving strength selection is to determine the best choice of the driving strength for each PTL cell without sacrificing the speed performance. Post-layout simulation shows that the synthesizer generates results with better area, speed and power performance compared with those with Artisan standard cell library which is popularly used in current cell-based design flow