An FPGA Implementation of Array LDPC Decoder

Author

Sha, Jin ; Gao, Minglun ; Zhang, Zhongjin ; Li, Li ; Wang, Zhongfeng

Author_Institution

Inst. of VLSI Design, Nanjing Univ.

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1675

Lastpage

1678

Abstract

Low-density parity-check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. This paper presents an FPGA implementation of array code based low-density parity-check code decoder. The advantages of the proposed architecture as compared to the fully parallel or partially parallel architecture are: less memory requirement, avoidance of complex global interconnects and its satisfying throughput. These advantages are derived from exploiting the well-defined structure of the parity check matrix of array code based LDPC codes

Keywords

codecs; error correction codes; field programmable gate arrays; parity check codes; FPGA implementation; LDPC decoder; error correcting codes; fully parallel architecture; low-density parity-check code decoder; parity check matrix; partially parallel architecture; Code standards; Error correction codes; Field programmable gate arrays; Iterative decoding; Logic; Parallel processing; Parity check codes; Sum product algorithm; Throughput; Very large scale integration; VLSI; array LDPC; decoder; design;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342088

Filename

4145732