Using genetic algorithm for slicing floorplan area optimization in circuit design

Author

Mani, Nallasamy ; Srinivasan, Bala

Author_Institution

Dept. of Electr. & Comput. Syst. Eng., Monash Univ., Clayton, Vic., Australia

Volume

3

fYear

1997

fDate

12-15 Oct 1997

Firstpage

2888

Abstract

The paper describes a combined genetic algorithm and slicing approach for floorplan area optimization. This approach helps the designer to explore the floorplan issues during the early stage of integrated circuit design. The slicing tree representation provides efficient tree traversal operations using recursion for obtaining area-efficient floorplans. Also, the slicing floorplan approach reduces the complexity of the resulting floorplan at the routing stage by eliminating the cyclic conflicts

Keywords

VLSI; circuit layout CAD; genetic algorithms; integrated circuit layout; trees (mathematics); IC design; circuit design; cyclic conflict elimination; efficient tree traversal operations; genetic algorithm; integrated circuit design; recursion; slicing floorplan area optimization; slicing tree representation; Australia; Circuit synthesis; Design engineering; Design optimization; Genetic algorithms; Integrated circuit synthesis; Integrated circuit technology; Routing; Systems engineering and theory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Systems, Man, and Cybernetics, 1997. Computational Cybernetics and Simulation., 1997 IEEE International Conference on

Conference_Location

Orlando, FL

ISSN

1062-922X

Print_ISBN

0-7803-4053-1

Type

conf

DOI

10.1109/ICSMC.1997.635433

Filename

635433