Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLAN

Author

Zhong, Wei ; Mao, Zhigang

Author_Institution

Microelectron. Center, Harbin Inst. of Technol.

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

1699

Lastpage

1702

Abstract

The conventional design of channel equalizer for IEEE 802.11a wireless local area network (WLAN) does not consider the different requirements of the adopted modulation schemes. In this paper, an adaptive-modulation-oriented channel equalizer and its VLSI architecture are developed. We analyze the different computation efforts of the modulation schemes and consider the system-level adaptive-modulation technique in the hardware implementation of channel equalizer. The adaptive-modulation-oriented channel equalizer applied to IEEE 802.11a can provide the appropriate architectures for different modulation schemes. In order to save the hardware resource, a dual-mode coordinate rotation digital computer (CORDIC) processor is designed, which is reused to accomplish rectangular-to-polar conversion and phase correction. The simulations and an implementation using FPGA technology validate the design

Keywords

OFDM modulation; VLSI; equations; field programmable gate arrays; integrated circuit design; wireless LAN; CORDIC processor; FPGA technology; IEEE 802.11a; OFDM; VLSI; WLAN; adaptive modulation; channel equalizer; coordinate rotation digital computer; orthogonal frequency-division multiplexing; AWGN; Computer architecture; Equalizers; Fast Fourier transforms; Field programmable gate arrays; Hardware; OFDM modulation; Transmitters; Very large scale integration; Wireless LAN; Orthogonal frequency-division multiplexing (OFDM); channel equalizer; wireless local area network (WLAN);

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342124

Filename

4145738