Title :
Using articulation nodes to improve the efficiency of finite-element based resistance extraction
Author :
vanGenderen, A.J. ; vanderMeiis, N.P.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol.
Abstract :
In this paper, we describe how we have improved the efficiency of a finite-element method for interconnect resistance extraction by introducing articulation nodes in the finite element mesh. The articulation nodes are found by detecting equipotential regions and lines in the interconnects. Without generating inaccuracies, these articulation nodes split the finite-element mesh into small pieces that can be solved independently. The method has been implemented in the layout-to-circuit extractor Space. All interconnect resistances of a circuit containing 63,000 transistors are extracted on an HP 9000/735 workstation in approximately 70 minutes
Keywords :
finite element analysis; HP 9000/735 workstation; Space; articulation nodes; digital CMOS circuits; equipotential regions; finite-element based resistance extraction efficiency; interconnect resistance extraction; layout-to-circuit extractor; Computational efficiency; Electric resistance; Equations; Finite element methods; Integrated circuit interconnections; Mesh generation; Permission; Very large scale integration; Wires; Workstations;
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-3294-6
DOI :
10.1109/DAC.1996.545674