A low energy two-step successive approximation algorithm for ADC design

This paper presents a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays is dramatically reduced compared to the traditional switching methods. Calibration registers are used to reduce the error of the most significant bits conversion due to the usage of a smaller capacitor array. Experiments were carried out on a 10-bit SAR-ADC designed using TSMC 0.18mum CMOS process. HSPICE simulations show that significant reduction in energy consumption is achieved using the proposed design.